Edge SoC Design Intern: Front-End & PPA Explorer

QUADRIC PTY LTD; Burlingame (CA); On-site; USD 69,000 - 79,000; Full time

Benefits offered by this job

Catered lunch daily

Downtown Burlingame office

Mentorship and project ownership

Job summary

Quadric is seeking an engineering intern to join the SoC design team in Burlingame, CA. You will gain hands-on experience on the GPNPU platform, assisting with subsystem development and integration tasks.

The role offers mentorship, exposure to PPA optimization, and collaboration with architects. You’ll develop practical SystemVerilog/Verilog skills and contribute to front-end design activities in a real-world project.

Qualifications

• Bachelor's/Master's/PhD in Electrical Engineering, Computer Engineering, or related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficient in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Responsibilities

• Support SoC Subsystem Development.
• Support PPA Optimization.
• Collaborate Across the Team.

Skills

SystemVerilog/Verilog

SoC Front-end design

Problem-solving

Clear technical communication

Python scripting

Education

Electrical Engineering / Computer Engineering (Bachelors/Masters/PhD)

Job description

Quadric is seeking an engineering intern to join the SoC design team in Burlingame, CA. You will gain hands-on experience on the GPNPU platform, assisting with subsystem development and integration tasks.

The role offers mentorship, exposure to PPA optimization, and collaboration with architects. You’ll develop practical SystemVerilog/Verilog skills and contribute to front-end design activities in a real-world project.