Senior Hardware Engineer — Edge AI SoC Equity & Flexible PTO

quadric technologies; Burlingame (CA); On-site; USD 150,000 - 220,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Equity

401(k)

Flexible PTO

Parental Leave

Catered lunch

Job summary

Quadric is redefining edge AI with a novel processor architecture and a senior chip design role based in Burlingame, CA. You will contribute across the design cycle, from architecture definition to RTL implementation, and drive PPA optimization.

The position favors a CA-based candidate who can work in our Burlingame office and participate in onsite meetings and events. The team seeks seasoned experts with front-end design experience and a strong HPC background.

Qualifications

• BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design
• Proficiency in SystemC, SystemVerilog, or Verilog
• Strong background in computer architecture
• Knowledge of design techniques for low power digital design
• Knowledge of VCS & Verilog/C Co-Sim
• Experience in data-parallel hardware design for high-performance computing
• Experience in FPGA design is a plus
• Experience in logic synthesis and performance modeling

Responsibilities

• Contribute to the definition of the processor architecture by understanding its applications
• Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
• Own Power, Performance & Area (PPA) optimization
• Contribute to timing closure through full product cycle (front end, back-end, tapeout)

Skills

Front-end CPU/GPU/ASIC design

Computer architecture

PPA optimization

SW/HW debugging

Low power design

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

SystemC

SystemVerilog

Verilog

VCS Co-Sim

Verilog/C co-simulation

FPGA design

Job description

Quadric is redefining edge AI with a novel processor architecture and a senior chip design role based in Burlingame, CA. You will contribute across the design cycle, from architecture definition to RTL implementation, and drive PPA optimization.

The position favors a CA-based candidate who can work in our Burlingame office and participate in onsite meetings and events. The team seeks seasoned experts with front-end design experience and a strong HPC background.