Senior SoC RTL Engineer - Edge AI & Low-Power Design

quadric technologies; Burlingame (CA); On-site; USD 170,000 - 230,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Equity

Flexible PTO

Parental Leave

401(k) Retirement Plan

Caltrain reimbursement

Job summary

Quadric is seeking a Staff SoC RTL Engineer in Burlingame, CA to drive SoC subsystem development, architecture definition, and IP integration across the end-to-end design flow. You will optimize power, performance, and area and guide timing closure for the next-generation edge AI platform.

Join a team building a pioneering GPNPU for real-time edge devices, collaborating across front-end and back-end teams, with a focus on SAS/SOC-level substates, IP integration, and customer-ready releases.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field
• Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience
• Proficiency in SystemVerilog or Verilog
• Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem
• Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation

Responsibilities

• Own SoC-level subsystem development and integration with third-party IP
• Contribute to SoC architecture definition by understanding application requirements
• Package designs for customer releases and iterate based on feedback
• Own PPA optimization strategies at the SoC level
• Apply low-power design techniques to optimize hardware efficiency
• Contribute to timing closure across front-end, back-end, and tapeout

Skills

SoC front-end design

SystemVerilog/Verilog

Computer architecture

SoC subsystems

3rd‑party IP integration

VCS & Verilog/C co-simulation

Low-power digital design

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

VCS

Verilog

Job description

Quadric is seeking a Staff SoC RTL Engineer in Burlingame, CA to drive SoC subsystem development, architecture definition, and IP integration across the end-to-end design flow. You will optimize power, performance, and area and guide timing closure for the next-generation edge AI platform.

Join a team building a pioneering GPNPU for real-time edge devices, collaborating across front-end and back-end teams, with a focus on SAS/SOC-level substates, IP integration, and customer-ready releases.