Edge SoC Design Intern - Build Next-Gen Subsystems (Onsite)

quadric technologies; Burlingame (CA); On-site; USD 69,000 - 79,000; Part time

Benefits offered by this job

Catered lunch

Downtown Burlingame office

Work culture focused on innovative dis

Job summary

Quadric in Burlingame, CA invites a hands-on internship on SoC design at the edge AI company. You will assist the SoC design team with subsystem development, third-party IP integration, and PPA optimization for the GPNPU platform, gaining exposure to front-end design methodologies and working with architects who define the chip.

Ideal candidates are pursuing a Bachelor's, Master's, or PhD in Electrical or Computer Engineering, familiar with SoC/ASIC front-end concepts, SystemVerilog or Verilog,

Qualifications

• Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficient in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Responsibilities

• Support SoC Subsystem Development: design and integrate SoC-level subsystems with third-party IP.
• Contribute to documentation of SoC architecture and application requirements.
• Support PPA Optimization: analyze and optimize Power, Performance, and Area at the SoC level.
• Get exposure to low-power digital design techniques and timing closure in front-end stages.
• Collaborate with SoC architects and designers to understand design intent and integration requirements.

Skills

SystemVerilog

Verilog

SoC front-end design

Debugging

Technical communication

Python

Education

Bachelor's/Master's/PhD in Electrical or Computer Engineering or related field

Job description

Quadric in Burlingame, CA invites a hands-on internship on SoC design at the edge AI company. You will assist the SoC design team with subsystem development, third-party IP integration, and PPA optimization for the GPNPU platform, gaining exposure to front-end design methodologies and working with architects who define the chip.

Ideal candidates are pursuing a Bachelor's, Master's, or PhD in Electrical or Computer Engineering, familiar with SoC/ASIC front-end concepts, SystemVerilog or Verilog,