Staff SoC RTL Engineer — PPA & Subsystem Lead

Quadric; Burlingame (CA); On-site; USD 175,000 - 230,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Equity in the company

401(k) retirement plan

Flexible PTO

Parental leave

Commuter support (Caltrain)

Catered lunch daily

Job summary

Quadric is hiring a Staff SoC RTL Engineer in Burlingame, CA. You will define SoC architecture, own subsystem development, and drive PPA optimization while integrating third-party IP. The role requires deep digital design expertise and a strong background in power-aware design.

You will contribute across front-end to tapeout, collaborating with a team on architectural decisions and customer-ready design releases. An advanced degree or extensive industry experience is valued.

Qualifications

• BS/MS/PhD in Electrical Engineering or related field.
• Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
• Proficiency in SystemVerilog or Verilog.
• Strong background in computer architecture, low-power digital design, and deep knowledge in at least one subsystem.
• Experience with SoC subsystems and third-party IP; working knowledge of VCS & Verilog/C Co-Simulation.

Responsibilities

• Own SoC-level subsystem development and integration with third-party IP (NoC, PCIe/UCIe, DDR, Security, etc.).
• Contribute to SoC architecture definition by understanding application requirements.
• Package designs for customer releases and iterate based on feedback.
• Own PPA optimization strategies at the SoC level; apply low-power design techniques.
• Contribute to timing closure across frontend, backend, and tapeout.
• Balance single-stream latency with scaled throughput.

Skills

SystemVerilog

Verilog

SoC/ASIC Front-end

Power/Low-power design

Computer architecture

3rd-party IP integration

VCS & Verilog/C Co-Simulation

IP/Subsystem ownership

Education

BS in Electrical Engineering

MS or PhD in Electrical Engineering

Tools

VCS

Job description

Quadric is hiring a Staff SoC RTL Engineer in Burlingame, CA. You will define SoC architecture, own subsystem development, and drive PPA optimization while integrating third-party IP. The role requires deep digital design expertise and a strong background in power-aware design.

You will contribute across front-end to tapeout, collaborating with a team on architectural decisions and customer-ready design releases. An advanced degree or extensive industry experience is valued.