Senior Hardware Architect – Edge AI & GPNPU Innovator

Quadric; Burlingame (CA); On-site; USD 150,000 - 220,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Equity

401(k) Retirement Plan

Flexible PTO

Catered lunch

Job summary

Quadric, based in Burlingame, California, is seeking a senior chip design engineer to drive processor architecture and RTL implementation across SystemC or SystemVerilog. You will own PPA optimization and contribute to timing closure through full front-end and back-end cycles.

You will collaborate with a high-impact team on a landmark edge AI processor, aligning architectural decisions with SW interfaces and customer needs, with regular onsite collaboration in CA.

Qualifications

• BS/MS or Ph.D. in Electrical or Computer Engineering with at least five years of CPU/GPU/ASIC front-end design.
• Proficiency in SystemC, SystemVerilog, or Verilog.
• Strong background in computer architecture.
• Knowledge of low power digital design techniques.
• Experience in data-parallel hardware design for high-performance computing.
• Experience in FPGA design is a plus.
• Experience in logic synthesis and performance modeling.

Responsibilities

• Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog.
• Own Power, Performance & Area (PPA) optimization.
• Contribute to timing closure through full product cycle (front end, back-end, tapeout).
• Collaborate with cross-functional teams on architecture and SW interfaces.

Skills

SystemC

SystemVerilog

Verilog

Computer architecture

Low power design

Data-parallel hardware

FPGA design

Performance modeling

VCS

Co-Simulation

Education

BS/MS or Ph.D. in Electrical or Computer Engineering

Tools

VCS

Verilog/C Co-Sim

Job description

Quadric, based in Burlingame, California, is seeking a senior chip design engineer to drive processor architecture and RTL implementation across SystemC or SystemVerilog. You will own PPA optimization and contribute to timing closure through full front-end and back-end cycles.

You will collaborate with a high-impact team on a landmark edge AI processor, aligning architectural decisions with SW interfaces and customer needs, with regular onsite collaboration in CA.