Staff SOC Physical Design Engineer

Qualcomm; Austin (TX); On-site; USD 161,179 - 210,000; Full time

Job summary

Qualcomm in Austin, Texas is seeking a Physical Design Engineer to lead high-speed DDR and graphics design efforts. This role demands a solid educational foundation in Electrical Engineering, with a preference for a Master's Degree and relevant experience. The position focuses on optimizing power utilization and conducting thorough physical verification checks.

The ideal candidate will have experience with floor planning, place and route, and timing analysis. The competitive salary range for this position is $161,179 to $210,000 per year, reflecting the critical nature of these contributions to our projects.

Qualifications

• Minimum of 3 years with a Master's Degree or 7+ years with a Bachelor's Degree in a related field.
• Experience in high-speed DDR and graphics design.
• Strong understanding of design-for-manufacturing and design-for-yield.

Responsibilities

• Lead physical design flow for high-speed DDR and graphics.
• Manage floor planning and clock tree synthesis.
• Perform physical verification checks and timing analysis.

Skills

Power utilization optimization

Micro-architecture

Physical verification

Timing analysis

Design reviews

Education

Master’s Degree in Electrical Engineering or related field

Bachelor’s Degree in Electrical Engineering or related field

Job description

General Summary

This individual leads the Physical Design Flow for high-speed DDR, graphics, and other SoC components, focusing on power utilization and optimization. The role synthesizes ambiguous or conflicting requirements and manages complex responsibilities across physical verification flows, micro‑architecture, SOC algorithm design and modeling, and methodology.

Responsibilities

• Floor planning
• Clock tree synthesis
• Place and route
• Power delivery network (PDN)
• Timing analysis and closure
• Perform physical verification checks (LVS, DRC, design‑for‑manufacturing & design‑for‑yield) at chip and block levels
• Provide schedules and support cross‑functional engineering effort to drive signoff closure for tapeout
• Act as a strong contributor at design reviews and project meetings, communicating and implementing a development plan

Qualifications

Preferred educational background includes a Master’s Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related field with at least 3 years of experience in a related occupation; or a Bachelor’s Degree (or foreign academic equivalent) in the same fields with 7+ years of progressive experience. Employer will accept any suitable combination of education, training or experience.

Pay Range

$161,179 – $210,000 per year.

EEO Employer Statement

Qualcomm is an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Disability Accommodation

Qualcomm provides reasonable accommodations for individuals with disabilities during the application and hiring process. If you need an accommodation, please contact disability‑[e-mail] or call the Qualcomm toll‑free number.

Contact

If you would like more information about this role, please contact Qualcomm Careers.