Lead SOC Physical Design Engineer

Nutanix; Austin (TX); On-site; USD 152,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced engineer to lead the physical design flow for high‑speed DDR and graphics within SoC projects. You will synthesize ambiguous requirements and drive placement, routing, PDN, and timing closure to tapeout.

The role emphasizes collaboration in cross‑functional teams, design reviews, and optimization for power and performance in cutting-edge technologies.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related field and 3 years of related experience.

Responsibilities

• Lead floor planning, clock tree synthesis, place and route, and PDN analysis for high‑speed SoC designs.
• Perform timing analysis and ensure closure to tapeout.
• Provide design reviews and communicate development plans across teams.

Skills

Physical design

Floor planning

Clock tree synthesis

Place and route

PDN analysis

Timing analysis

Power optimization

SoC architecture

Education

Master's degree in Electrical/Computer Engineering or CS

Job description

Qualcomm Technologies, Inc. is seeking an experienced engineer to lead the physical design flow for high‑speed DDR and graphics within SoC projects. You will synthesize ambiguous requirements and drive placement, routing, PDN, and timing closure to tapeout.

The role emphasizes collaboration in cross‑functional teams, design reviews, and optimization for power and performance in cutting-edge technologies.