Advanced-Node SoC Physical Design Lead (7/5/3nm)

SK hynix memory solutions; San Jose (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

Medical, dental, vision

Life insurance

401(k) match

Cafeteria

Onsite gym

Job summary

SK hynix memory solutions in San Jose seeks a Sr. Staff / Principal Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will work closely with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success.

You will mentor junior engineers, define team methodologies, and drive tapeouts across 7nm/5nm/3nm nodes, balancing performance, power, and area in a fast-paced environment.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering (Master's preferred).
• 8+ years of hands-on ASIC physical design experience with tapeout success.
• Expert-level proficiency in synthesis, placement, CTS, routing using Synopsys/Cadence tools.
• Deep knowledge of STA and PrimeTime signoff with multi-corner/multi-mode closure.
• Experience with Calibre DRC/LVS/ERC and IR drop/EM analysis.

Responsibilities

• Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced nodes (7nm/5nm/3nm).
• Drive timing closure and signoff using PrimeTime and advanced analyses (SI, POCV, crosstalk, ECO).
• Perform RC extraction and ensure strong STA correlation; own physical verification signoff with Calibre.
• Develop and optimize flows and automation scripts; mentor junior engineers and coordinate cross-functional tapeouts.

Skills

ASIC physical design

Synthesis

Timing closure

Mentoring/leadership

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's preferred

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

Mentor Calibre

StarRC/Quantus

Ansys RedHawk

Python/Tcl/Perl

Job description

SK hynix memory solutions in San Jose seeks a Sr. Staff / Principal Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will work closely with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success.

You will mentor junior engineers, define team methodologies, and drive tapeouts across 7nm/5nm/3nm nodes, balancing performance, power, and area in a fast-paced environment.