Senior Physical Design Engineer - SoC & Tapeout Lead

SKHMS Corporation; San Jose (CA); Hybrid; USD 160,000 - 220,000; Full time

Job summary

SK hynix memory solutions is seeking a Sr. Staff Physical Design Engineer to lead RTL-to-GDS implementation for advanced-node SoCs.

You will guide synthesis, placement, CTS, and routing while collaborating with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success. Requirements include 6+ years in ASIC physical design, strong expertise in STA and PrimeTime, and hands-on experience with Calibre for DRC/LVS/ERC.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred).
• 6+ years of hands-on ASIC physical design with proven tapeout success.
• Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools.
• Deep knowledge of static timing analysis (STA) and PrimeTime signoff, multi-corner/multi-mode closure.
• Experience with Calibre (DRC, LVS, ERC) and IR drop/EM analysis using RedHawk.

Responsibilities

• Lead physical design implementation from synthesis through GDS for high-performance blocks or full-chip SoC designs in advanced process nodes (7nm, 5nm, 3nm).
• Optimize synthesis, placement, CTS, and routing using P&R tools (Synopsys ICC2/Fusion Compiler or Cadence Innovus).
• Drive timing closure and signoff using PrimeTime, including SI, AOCV/POCV, crosstalk, and ECO implementation.
• Perform RC extraction using StarRC or Quantus and ensure strong correlation between extraction and STA results.
• Own physical verification signoff with Calibre, resolving DRC, LVS, ERC, and antenna violations.
• Conduct power integrity analysis using Ansys RedHawk, including IR drop and EM analysis; optimize power grid/decap.
• Develop and maintain physical design flows and automation scripts (Tcl, Perl, Python).
• Mentor junior engineers and collaborate across teams to achieve tapeout schedules.

Skills

ASIC physical design

Tapeout experience

Synthesis and routing

PrimeTime signoff

Calibre verification

Education

Bachelor's in Electrical/Computer Eng (Master's preferred)

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

Job description

SK hynix memory solutions is seeking a Sr. Staff Physical Design Engineer to lead RTL-to-GDS implementation for advanced-node SoCs.

You will guide synthesis, placement, CTS, and routing while collaborating with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success. Requirements include 6+ years in ASIC physical design, strong expertise in STA and PrimeTime, and hands-on experience with Calibre for DRC/LVS/ERC.