Senior SoC Physical Design Architect — Top Level

Apple; Beaverton (OR); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple is seeking a highly experienced chip designer to lead complete ASIC design from netlist to tapeout in Beaverton, Oregon. You will collaborate with FE and physical design teams, drive floorplanning, timing, and IP integration, and resolve physical design challenges for multi‑GHz SoCs with >20M gates.

A 10+ year track record in advanced IC design is required. Strong communication and project planning are essential.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.

Responsibilities

• Implement complete chip design from netlist to tapeout.
• Collaborate with FE and physical design teams on architecture and methodologies.
• Lead place-and-route activities and establish milestones.
• Resolve design and flow issues in physical design.

Skills

ASIC integration

Floorplanning

Clock distribution

Power distribution

IO planning

Global timing

IP integration

P&R flows

CAD tools

Physical verification

Thermal mgmt

Education

BS degree in EE/CS

Tools

CAD tools

Job description

Apple is seeking a highly experienced chip designer to lead complete ASIC design from netlist to tapeout in Beaverton, Oregon. You will collaborate with FE and physical design teams, drive floorplanning, timing, and IP integration, and resolve physical design challenges for multi‑GHz SoCs with >20M gates.

A 10+ year track record in advanced IC design is required. Strong communication and project planning are essential.