Senior Physical Design Engineer – High-Performance PHY/SOC

Apple Inc.; Beaverton (OR); On-site; USD 185,000 - 325,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Beaverton, Oregon is seeking a seasoned Physical Design Engineer to drive high-performance PHY designs from RTL to GDSII.

You will collaborate across architecture, CAD, timing and logic teams to deliver competitive silicon. Responsibilities include building block and full-chip floorplans, placing and routing to meet timing and power goals, generating timing constraints, and debugging LVS/DRC issues while contributing to CAD methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering; 10+ years experience preferred.
• Deep PHY/SOC design experience and HDL knowledge.
• Experience with Physical Design standards: synthesis, floor-planning, and Place&Route.

Responsibilities

• Perform physical design from RTL to GDSII delivery.
• Generate block/chip level timing constraints and floor-plans.
• Place and route to meet timing, area, and power constraints.
• Develop and implement ECOs to fix timing, noise, and EM/IR violations.
• Support CAD and physical design methodologies for correct-by-construction designs.

Skills

PHY/SOC design

Physical design standards

Power-grid & clock specs

Physical construction & verification

Verilog HDL

Perl/Tcl scripting

Extraction & STA

LVS/DRC debugging

Synthesis tools

SoC architecture

Education

Bachelor of Science in Electrical Engineering

Tools

Synthesis tools

STA tools

LVS/DRC tools

Job description

Apple Inc. in Beaverton, Oregon is seeking a seasoned Physical Design Engineer to drive high-performance PHY designs from RTL to GDSII.

You will collaborate across architecture, CAD, timing and logic teams to deliver competitive silicon. Responsibilities include building block and full-chip floorplans, placing and routing to meet timing and power goals, generating timing constraints, and debugging LVS/DRC issues while contributing to CAD methodologies.