SoC Physical Design Engineer, Top Level

Apple; Beaverton (OR); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple is seeking a highly experienced chip designer to lead complete ASIC design from netlist to tapeout in Beaverton, Oregon. You will collaborate with FE and physical design teams, drive floorplanning, timing, and IP integration, and resolve physical design challenges for multi‑GHz SoCs with >20M gates.

A 10+ year track record in advanced IC design is required. Strong communication and project planning are essential.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.

Responsibilities

• Implement complete chip design from netlist to tapeout.
• Collaborate with FE and physical design teams on architecture and methodologies.
• Lead place-and-route activities and establish milestones.
• Resolve design and flow issues in physical design.

Skills

ASIC integration

Floorplanning

Clock distribution

Power distribution

IO planning

Global timing

IP integration

P&R flows

CAD tools

Physical verification

Thermal mgmt

Education

BS degree in EE/CS

Tools

CAD tools

Job description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!

In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.

• Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
• Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
• Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.

Minimum Qualifications

Minimum BS and 10+ years of relevant industry experience

Preferred Qualifications

• Needs to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
• Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
• Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required.
• Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies.
• A detailed understanding of database management issues is required.
• From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required.
• Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.