Top-Level SoC Physical Design Engineer

Apple Inc.; Seattle, Northern (WA, KY); Hybrid; USD 175,000 - 309,000; Full time

Job summary

Apple Inc. in Seattle seeks a senior chip design lead responsible for implementing complete chip design from netlist to tapeout. You will work with FE and physical design teams to drive architecture, timing, and physical convergence, across multi-domain environments.

The role requires a BS with 10+ years in ASIC/SoC design, familiarity with floorplanning, clock/power distribution, and IP integration, and you will influence layout decisions and verification flows. Base salary range shown applies.

Qualifications

• BS degree plus 10+ years in chip/ASIC design.
• Experience with floorplanning, clock and power distribution, IP integration.

Responsibilities

• Work with FE to understand chip architecture and drive physical design.
• Drive place and route and track milestones across domains.
• Resolve design and flow issues related to physical design.

Skills

ASIC integration

Floorplanning

Clock distribution

Power distribution

Global signal planning

I/O planning

Hard IP integration

SoC issues

Multiple voltage domains

Clock domains

ESD strategies

Mixed-signal integration

Package interactions

Hierarchical design

Top-down design

Budgeting

Timing

Physical convergence

IP requirements

P&R flows

Global timing verification

Physical design verification

Design for Yield

Manufacturability

Multi Vt strategies

Thermal management

CAD tools

Education

Bachelor of Science in a relevant field

Tools

Floorplanning tools

P&R flows

Global timing verification

Physical design verification

Job description

Apple Inc. in Seattle seeks a senior chip design lead responsible for implementing complete chip design from netlist to tapeout. You will work with FE and physical design teams to drive architecture, timing, and physical convergence, across multi-domain environments.

The role requires a BS with 10+ years in ASIC/SoC design, familiarity with floorplanning, clock/power distribution, and IP integration, and you will influence layout decisions and verification flows. Base salary range shown applies.