Senior SOC Architect: Fabric, Cache & DRAM Controller

Samsung Research America (SRA); Mountain View (CA); On-site; USD 197,800 - 296,600; Full time

Job summary

Samsung Research America in Mountain View seeks a SOC Architect for Fabric, System Cache and DRAM Controller to shape next generation SoCs. This highly visible role leads individual and team contributions to Fabric, System cache and DRAM controller sub‑system architecture, interface, performance and power tradeoffs.

The position requires 12+ years in SOC/ASIC design and architecture with strong memory systems expertise and ARM interface knowledge.

Qualifications

• 12+ years of SOC/ASIC design and architecture experience.
• Direct >9 years in Fabric, System Cache, DRAM controller architecture.
• Deep memory controller and memory scheduling knowledge.
• Familiar with ARM bus infrastructure (ACE/AXI/AHB).
• Knowledge of JEDEC standards (LPDDR, DDR, HBМ).
• Ability to analyze memory bandwidth, latency, power vs. area tradeoffs.

Responsibilities

• Lead architectural and microarchitectural features for Fabric, System Cache, and DRAM controller.
• Develop proposals to boost power and performance for next generation SOCs.
• Evaluate architecture benefits with SoC Architects and communicate results across SW, HW, and architecture teams.
• Perform high-level performance modeling and simulations of features and workloads.
• Collaborate with silicon bring-up and product teams to verify delivered performance.
• Document interfaces and drive architectural readiness across the SOC, Driver, OS, and System teams.

Skills

Fabric Architecture

System Cache

DRAM Controller

Memory System

Memory Scheduling

QoS

ARM ACE/AXI/AHB

JEDEC LPDDR/DDR/HBM

Power & Performance Tradeoffs

Performance Modeling

Team Leadership

SoC Architecture

Education

BSc, Masters, or PhD in Computer Science/Engineering

Tools

BookSim Simulator

Platform Architect

Job description

Samsung Research America in Mountain View seeks a SOC Architect for Fabric, System Cache and DRAM Controller to shape next generation SoCs. This highly visible role leads individual and team contributions to Fabric, System cache and DRAM controller sub‑system architecture, interface, performance and power tradeoffs.

The position requires 12+ years in SOC/ASIC design and architecture with strong memory systems expertise and ARM interface knowledge.