Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

Samsung Research America; Mountain View (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

Samsung Research America in Mountain View is seeking a Senior Engineer to lead the architecture of next-gen SoCs. This role involves guiding innovative features for the memory subsystem and collaborating across teams to deliver architecture proposals.

The ideal candidate has at least 3 years in SoC design and extensive knowledge of memory systems and computer architecture. Experience with JEDEC standards is essential.

Qualifications

• 3+ years of experience in SoC or ASIC design and architecture.
• Prior experience in Fabric, System Cache, DRAM controller Architecture is required.
• Understanding of memory scheduling and QoS.

Responsibilities

• Guide on development of innovative Fabric, System cache, and DRAM controller features.
• Evaluate architecture proposal benefits with SoC Architects team.
• Direct performance modeling studies for next generation microarchitecture.

Skills

SoC or ASIC design and architecture

Memory controller architecture

ARM bus infrastructure

JEDEC standards (LPDDR, DDR, HBM)

Performance modeling/simulation

Education

BSc, Masters, or PhD in Computer Science/Engineering

Tools

BookSim Simulator

Platform Architect

Job description

Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

Lab Summary: The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high‑performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.

Position Summary: We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands‑on role leading individual and team contributions to Fabric, System cache and DRAM controller sub‑system architecture, interface, performance and power tradeoffs.

Position Responsibilities

• Guide on development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs
• Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets
• Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership)
• Perform high‑level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex use cases
• Direct and orchestrate performance modeling, and studies to support inclusion of these features in the next generation “Fabric, System cache and DRAM controller” microarchitecture based on performance, area or power improvement
• Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
• Collaborate with silicon bring‑up and product teams to verify and debug the proposal and its delivered performance
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations

Required Skills

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
• 3+ years of experience in SOC or ASIC design and architecture
• Prior direct experience (≥7 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required
• Understanding of memory controller architecture, memory scheduling, prioritization and QoS
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
• Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

Special Attributes

• Experience with BookSim Simulator
• Experience with Platform Architect

Essential Job Functions

This position will be performed in an office setting. The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.

Equal Employment Opportunity Statement

Samsung Research America is an equal‑opportunity employer committed to complying with all Federal, State and local laws related to the employment of qualified individuals with disabilities. The company encourages a diverse workforce and provides reasonable accommodations to qualified candidates.