Senior SoC DV Engineer - DDR & Fabric NoC

Tenstorrent

California (MO)

Hybrid

USD 100,000 - 500,000

Full time

14 days+
Application generator

A complete application in a minute — tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, focusing on the Compute Subsystem, DDR memory subsystem, and Fabric NoC. Hybrid role based in Boston, MA; Toronto, ON; or Santa Clara, CA; multiple experience levels welcomed.

Candidate will develop verification environments, write test scenarios, analyze coverage, and drive signoff for major features while leveraging scripting and automation tools. Equal opportunity employer.

Qualifications

  • Expertise in UVM, SystemVerilog, and coverage-driven verification.
  • Experience verifying compute subsystems, DDR controllers, and interconnects.
  • Proficiency with verification automation tools and scripting.

Responsibilities

  • Develop and own scalable verification environments for Beowulf SoC CSS, DDR, and Fabric NoC across subsystem and full-SoC levels.
  • Write, refine, and execute test scenarios for compute operation, memory initialization and traffic, coherency, routing, and data movement.
  • Analyze coverage gaps, debug failures, drive root-cause analysis, and collaborate with architecture, RTL, firmware, emulation, and system teams.
  • Drive verification planning, regression quality, coverage closure, and signoff for major SoC features.
  • Automate verification flows using scripting, reusable infrastructure, and AI productivity tools.
  • Mentor engineers and contribute to verification methodology and design-for-verification improvements.

Skills

UVM SystemVerilog
Coverage-driven verification
Assertions
Subsystem-level debugging
Python
C/C++
Tcl
CocoTB

Tools

CocoTB
Tcl

Job description

Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, focusing on the Compute Subsystem, DDR memory subsystem, and Fabric NoC. Hybrid role based in Boston, MA; Toronto, ON; or Santa Clara, CA; multiple experience levels welcomed.

Candidate will develop verification environments, write test scenarios, analyze coverage, and drive signoff for major features while leveraging scripting and automation tools. Equal opportunity employer.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior SoC DV Engineer – Pre-Silicon DDR/NoC (Hybrid)
Senior SoC DV Engineer – Pre-Silicon DDR/NoC (Hybrid)

Tenstorrent Inc. • Boston (MA), Santa Clara (CA)

Hybrid
USD 100,000 - 500,000
Sr. Engineer, SoC Design Verification
Sr. Engineer, SoC Design Verification

Tenstorrent Inc. • Boston (MA), Santa Clara (CA)

On-site
USD 100,000 - 500,000
Sr. Engineer, SoC Design Verification
Sr. Engineer, SoC Design Verification

Tenstorrent • California (MO)

Hybrid
USD 100,000 - 500,000
Senior CPU Verification Lead — Hybrid, Mentoring & DV Strategy
Senior CPU Verification Lead — Hybrid, Mentoring & DV Strategy

Tenstorrent • Boston (MA), Northern (KY)

Hybrid
USD 100,000 - 500,000
Lead Silicon Verification Architect (DDR5/NoC/HBM)
Lead Silicon Verification Architect (DDR5/NoC/HBM)

AMD • San Jose (CA)

On-site
USD 180,000 - 260,000
Design Verification Engineers DDR
Design Verification Engineers DDR

RAPS Consulting Inc • Edison (NJ)

On-site
USD 100,000 - 130,000
Senior Design Verification Architect - Memory/NoC Lead
Senior Design Verification Architect - Memory/NoC Lead

AMD • San Jose (CA)

On-site
USD 180,000 - 240,000
AMD Benefits at a glance
Staff Engineer, SoC Verification MultiChip
Staff Engineer, SoC Verification MultiChip

Tenstorrent • California (MO)

On-site
USD 100,000 - 140,000
Competitive compensation package
Benefits
Equal opportunity employer
Principal DV Engineer – Hybrid (Memory Controller)
Principal DV Engineer – Hybrid (Memory Controller)

Rambus.com • Hillsboro (OR)

Hybrid
USD 127,000 - 237,000
DDR Design Verification Engineer — On-Site San Jose
DDR Design Verification Engineer — On-Site San Jose

SiMa Technologies, Inc. • San Jose (CA)

Hybrid
USD 176,000 - 282,000
Private company equity