DDR Design Verification Engineer — On-Site San Jose

SiMa Technologies, Inc.; San Jose (CA); Hybrid; USD 176,000 - 282,000; Full time

Benefits offered by this job

Private company equity

Job summary

SiMa Technologies, Inc. is seeking a DDR Design Verification Engineer to define and develop verification methodologies for the MLSoC DDR block.

You will create DDR test plans, test benches, and test cases, driving verification across LPDDR IP and DDR-IO interfaces in a collaborative lab setting. You will work with Architecture, RTL/uArch, and cross-functional teams to verify functionality, performance, and coverage, with the opportunity to contribute to DDR bring-up on silicon in our San Jose

Qualifications

• 10+ years in SoC design verification or 8+ years with MS in CS/EE.
• Proficient in SystemVerilog, UVM, constrained random, coverage-driven verification.
• DDR/LPDDR IP verification and DDR-IO verification experience required; LPDDR5 knowledge preferred.

Responsibilities

• Develop DDR verification methodology, test plans, benches, and test cases.
• Execute plans to verify MLSoC DDR functionality, performance, and coverage.
• Collaborate with Architecture, RTL/uArch, and cross-functional teams; bring-up on silicon.

Skills

SystemVerilog

UVM

Constrained random

Coverage driven verification

DDR/LPDDR IP verification

Python/Perl scripting

Test bench development

Debugging

Education

BS in CS/EE

MS in CS/EE

Job description

SiMa Technologies, Inc. is seeking a DDR Design Verification Engineer to define and develop verification methodologies for the MLSoC DDR block.

You will create DDR test plans, test benches, and test cases, driving verification across LPDDR IP and DDR-IO interfaces in a collaborative lab setting. You will work with Architecture, RTL/uArch, and cross-functional teams to verify functionality, performance, and coverage, with the opportunity to contribute to DDR bring-up on silicon in our San Jose