Principal DV Engineer – Hybrid (Memory Controller)

Rambus.com; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Job summary

Rambus seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP Verification team in Hillsboro, Oregon. The role involves pre-silicon RTL verification for DDR, HBM and GDDR DRAM controllers, with hybrid onsite flexibility.

Responsibilities include testbench creation, coverage planning, regression testing, and verification environment scripting. Required: 10+ years HDL verification with SystemVerilog and DDR experience.

Qualifications

• Bachelor's degree or above in EE/CS with 10+ years HDL design and verification experience.
• Strong SystemVerilog testbench skills and RTL fluency required.
• Prior DDR DRAM technology knowledge is highly preferred.

Responsibilities

• Testbench and test sequence development for verification of new controller technologies and features.
• Functional coverage planning and test suite augmentation to achieve functional coverage.
• Regression test development, debug/triage and test environment improvement.
• Development and support of verification environments and scripting.

Skills

SystemVerilog testbench

Verilog/SystemVerilog RTL fluency

Python scripting

TCL scripting

DDR DRAM familiarity

Education

Bachelor's Degree in EE/CS

Job description

Rambus seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP Verification team in Hillsboro, Oregon. The role involves pre-silicon RTL verification for DDR, HBM and GDDR DRAM controllers, with hybrid onsite flexibility.

Responsibilities include testbench creation, coverage planning, regression testing, and verification environment scripting. Required: 10+ years HDL verification with SystemVerilog and DDR experience.