Senior SoC Digital Design Lead — RTL & Tapeout

Unconventional AI; Mountain View (CA); On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals in Palo Alto

Job summary

Unconventional AI in Mountain View seeks a Member of Technical Staff, Digital Design Engineer to join a small, multi-disciplinary R&D team at the intersection of AI, physics, and computer architecture. You will drive invention, prototyping, and validation of core components of our novel computing platform.

Responsibilities include hands-on RTL design, synthesis, DV support, and mentoring junior engineers to advance design methodologies and quality assurance across the team, with emphasis on

Qualifications

• B.S. or M.S. in Electrical/Computer Engineering or related field.
• 8+ years of industry experience in digital ASIC/SoC design.
• Proficiency with Verilog RTL coding and digital design fundamentals.
• Familiarity with standard EDA tools for simulation, synthesis, linting, and CDC analysis.

Responsibilities

• Lead detailed micro-architecture definition and top-level integration of digital blocks (CPU, memory subsystems, interfaces).
• Own integration of third-party IP into the SoC fabric.
• Provide mentorship to junior digital design engineers and contribute to design methodologies and QA processes.
• Drive hands-on RTL design for timing-critical blocks and interfaces to meet PPA targets.
• Perform synthesis and formal verification to ensure routability and frequency targets; create timing constraints.

Skills

Verilog RTL

Digital design

EDA tools

Communication

Leadership

Education

B.S./M.S. in Electrical or Computer Engineering

Tools

Synthesis tools

Simulation tools

Job description

Unconventional AI in Mountain View seeks a Member of Technical Staff, Digital Design Engineer to join a small, multi-disciplinary R&D team at the intersection of AI, physics, and computer architecture. You will drive invention, prototyping, and validation of core components of our novel computing platform.

Responsibilities include hands-on RTL design, synthesis, DV support, and mentoring junior engineers to advance design methodologies and quality assurance across the team, with emphasis on