Senior SoC DFT Engineer - Silicon Test & Debug

Apple Inc.; Waltham (MA); On-site; USD 154,600 - 274,900; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Retirement benefits

Employee stock programs

Tuition reimbursement

Job summary

A leading technology company is seeking an experienced DFT engineer in Waltham, Massachusetts. The role involves developing DFT architecture, collaborating with design and verification teams, and enhancing test vector coverage. Candidates should possess at least 10 years of relevant experience and knowledge of industry standards like ATPG and JTAG. The position offers competitive compensation and comprehensive benefits including stock programs, medical coverage, and educational reimbursement.

Qualifications

• Minimum of 10 years relevant industry experience required.
• Experience in developing DFT specifications.
• Proficient in debugging compressed ATPG patterns.

Responsibilities

• Develop and implement DFT architecture for semiconductor design.
• Work with the DV team to verify DFT implementations.
• Generate structural test vectors and analyze coverage.

Skills

DFT architecture knowledge

Test pattern generation

Silicon debugging

Knowledge of Verilog/VHDL

Design verification methodologies

Education

Bachelor's degree in a relevant field

Tools

Simulators

Waveform debugging tools

Job description

A leading technology company is seeking an experienced DFT engineer in Waltham, Massachusetts. The role involves developing DFT architecture, collaborating with design and verification teams, and enhancing test vector coverage. Candidates should possess at least 10 years of relevant experience and knowledge of industry standards like ATPG and JTAG. The position offers competitive compensation and comprehensive benefits including stock programs, medical coverage, and educational reimbursement.