Senior CPU DFT Engineer - ASIC Test & Debug (DFT/ATPG)

Qualcomm; Santa Clara (CA); On-site; USD 142,200 - 213,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus

Annual RSU grants

Comprehensive benefits package

Job summary

A leading tech company is seeking a DFT Engineer to work closely with chip architects and designers on mixed signal and digital VLSI designs. The role involves creating test vectors, validating DFT requirements, and ensuring high test coverage. Ideal candidates will have extensive experience in digital ASIC design, proficiency in Verilog or VHDL, and expertise with Mentor Tessent tools. This position offers a competitive salary range of $142,200 to $213,400, along with a comprehensive benefits package.

Qualifications

• 5+ years of practical experience in relevant fields.
• Familiarity with ASIC test, DFT, and debug techniques.
• Experience managing large design verification.

Responsibilities

• Create test vectors or oversee their creation.
• Validate DFT requirements are being met.
• Work with designers to increase test coverage.

Skills

Digital ASIC design

Verilog

VHDL

TCL

Perl/Python

Scripting

Education

BA/BS in Electrical/Computer Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Mentor Tessent tools

Job description

A leading tech company is seeking a DFT Engineer to work closely with chip architects and designers on mixed signal and digital VLSI designs. The role involves creating test vectors, validating DFT requirements, and ensuring high test coverage. Ideal candidates will have extensive experience in digital ASIC design, proficiency in Verilog or VHDL, and expertise with Mentor Tessent tools. This position offers a competitive salary range of $142,200 to $213,400, along with a comprehensive benefits package.