Senior DFT Design Engineer III Scan/ATPG MBIST JTAG On-Site

Arrow Electronics; San Jose (CA); On-site; USD 95,900 - 170,500; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with Matching Contributions

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Job summary

A leading global electronics firm is looking for a Design For Test Engineer III in San Jose, CA. You will handle DFT implementation for advanced networking chips, along with responsibilities including RTL checks, pattern generation, and silicon debugging. Ideal candidates will have 5-7 years of experience in DFT, familiarity with multiple tools such as Mentor Tessent and VCS, and a degree in Microelectronics or Electronics. Attractive benefits package including medical insurance, 401k matching, and tuition reimbursement is offered.

Qualifications

• 5 – 7 years of experience in DFT and relevant fields.
• Experience in multi-million gate count SoCs.
• Excellent communication skills are a must.

Responsibilities

• Responsible for DFT implementation for networking chips.
• Conduct RTL checks for scan-insertion compatibility.
• Generate ATPG patterns for both Compressed and Uncompressed Mode.

Skills

DFT implementation

Scan-Insertion

ATPG

Pattern Simulations

MBIST Insertion

Scripting with Perl

Low power DFT

Education

B. Tech or M. Tech in Microelectronics/Electronics

Tools

Mentor Tessent

Synopsys Spyglass

Cadence Modus

Synopsys Tetramax

VCS

Verdi

Job description

A leading global electronics firm is looking for a Design For Test Engineer III in San Jose, CA. You will handle DFT implementation for advanced networking chips, along with responsibilities including RTL checks, pattern generation, and silicon debugging. Ideal candidates will have 5-7 years of experience in DFT, familiarity with multiple tools such as Mentor Tessent and VCS, and a degree in Microelectronics or Electronics. Attractive benefits package including medical insurance, 401k matching, and tuition reimbursement is offered.