Senior SoC Architect: Fabric, Cache & DRAM Controller

Samsung Research America; Mountain View (CA); On-site; USD 272,489,280 - 408,596,160; Full time

Job summary

Samsung Research America is seeking a Senior Staff Engineer to lead architecture of memory subsystem and interconnect in next-generation SoCs. The role combines fabric, system cache and DRAM controller design with performance and power tradeoffs across workloads.

You will guide architectural decisions, perform high-level modeling, and collaborate with silicon bring-up, software and hardware teams to deliver validated features for high-performance Galaxy-class devices.

Qualifications

• 12+ years of SOC/ASIC design and architecture experience.
• Deep memory subsystem and memory controller know‑how.
• Experience with fabric/interconnect architectures and QoS.
• Familiarity with JEDEC standards (LPDDR, DDR, HBM) is a plus.

Responsibilities

• Guide development of Fabric, System cache and DRAM controller features to boost performance and power efficiency.
• Propose architectures for next‑gen SOCs across new and existing markets.
• Evaluate proposals with cross‑functional teams and communicate results to SW/HW/Leadership.
• Perform high‑level performance modeling and analysis for workloads and benchmarks.
• Lead studies to justify architecture in microarchitecture with performance/area/power tradeoffs.
• Deliver architecture specs to design teams and articulate across audiences.
• Collaborate with silicon bring‑up and product teams to verify delivered performance.

Skills

SOC/ASIC design

Memory controller architecture

Fabric/Interconnect

Performance modeling

ARM ACE/AXI/AHB

Power optimization

JEDEC LPDDR/DDR/HBM

Education

Bachelor's/Master's/PhD in CS/Engineering

Tools

BookSim Simulator

Platform Architect

Job description

Samsung Research America is seeking a Senior Staff Engineer to lead architecture of memory subsystem and interconnect in next-generation SoCs. The role combines fabric, system cache and DRAM controller design with performance and power tradeoffs across workloads.

You will guide architectural decisions, perform high-level modeling, and collaborate with silicon bring-up, software and hardware teams to deliver validated features for high-performance Galaxy-class devices.