Senior Silicon Packaging Architect: End-to-End IC Packaging

Intel Corporation; Phoenix (AZ); On-site; USD 164,000 - 312,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in the United States (Arizona, Phoenix) seeks a Silicon Packaging Design Architect to lead end-to-end packaging solutions across electrical, mechanical, and cost constraints. You will collaborate with silicon, hardware, and package teams to ensure robust production transitions and drive packaging innovations.

Senior engineering role focusing on advanced packaging technologies, 3D IC design standards, and continuous improvement of packaging processes and tools.

Qualifications

• Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 6+ years of experience.
• Master's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 4+ years of experience.
• Ph.D. in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 2+ years of experience.
• 2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
• Experience with Cadence Allegro and Mentor Xpedition platform tools.
• Knowledge of assembly processes, test methodologies, and characterization techniques.

Responsibilities

• Translate product requirements into detailed package architecture specifications.
• Drive technology tradeoff decisions to ensure packages meet electrical, mechanical, thermal, and reliability standards.
• Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions.
• Oversee end-to-end package development, including design, procedures, and quality improvements.
• Troubleshoot packaging designs and resolve materials/process issues with cost-conscious solutions.
• Implement co-design strategies between silicon and board design teams to optimize product performance and cost.

Skills

Semiconductor fabrication

Electromagnetic simulation

Assembly processes

Education

Bachelor's degree in EE/ME/ChemE/Materials Science

Master's degree in EE/ME/ChemE/Materials Science

Ph.D. in EE/ME/ChemE/Materials Science

Tools

Mentor

Cadence

SPICE

Ansys

Job description

Intel Corporation in the United States (Arizona, Phoenix) seeks a Silicon Packaging Design Architect to lead end-to-end packaging solutions across electrical, mechanical, and cost constraints. You will collaborate with silicon, hardware, and package teams to ensure robust production transitions and drive packaging innovations.

Senior engineering role focusing on advanced packaging technologies, 3D IC design standards, and continuous improvement of packaging processes and tools.