Advanced Semiconductor Packaging Research Engineer

Intel; Phoenix (AZ); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Hybrid work model

Job summary

Intel is seeking a Semiconductor Packaging Research Engineer to drive technology research in advanced packaging and heterogeneous integration in the Phoenix area. The role involves evaluating architectures, materials, interconnects, and reliability, with opportunities to contribute to DOE experiments and IP development.

Qualified candidates have graduate degrees in engineering and 1+ years of experience in packaging research or related areas, including modeling or process integration.

Qualifications

• Master's or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field.
• 1+ years' experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
• 1+ years' experience in one or more of the following areas: process integration, research vehicle execution, DOE, defect/yield learning, reliability, model development & validation, or multi-physics simulation.
• 1+ years' experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.

Responsibilities

• Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer, and die-to-die interconnects.
• Drive either process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness.
• For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
• For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data.
• Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, design guidance, IP, publications, and development-transfer inputs.
• Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.

Skills

Packaging research

DOE

Modeling/simulation

Heterogeneous integration

Education

Master's or Ph.D. in Engineering

Tools

ANSYS

Abaqus

COMSOL

MATLAB

Python

Job description

Intel is seeking a Semiconductor Packaging Research Engineer to drive technology research in advanced packaging and heterogeneous integration in the Phoenix area. The role involves evaluating architectures, materials, interconnects, and reliability, with opportunities to contribute to DOE experiments and IP development.

Qualified candidates have graduate degrees in engineering and 1+ years of experience in packaging research or related areas, including modeling or process integration.