Senior Silicon Verification Engineer: Drive Bug-Free SoCs

Google; Mountain View (CA); On-site; USD 150,000 - 223,000; Full time

Job summary

Google's Devices & Services team in Mountain View, CA seeks a Senior Design Verification Engineer to drive verification of digital blocks for custom silicon. You will plan verification strategies, build robust test benches, and mentor junior engineers.

Requirements include a Bachelor's in EE/CE/CS, 5 years in verification with UVM/SystemVerilog, and experience with test benches and environments. Preferred: advanced degrees and ARM/RISC-V verification experience.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
• Experience developing and maintaining verification test benches, test cases, and test environments.

Responsibilities

• Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA) and formal tools.
• Debug tests with design engineers to deliver design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Participate with architecture, design teams, and other teams in defining the overall verification strategy of our SoCs.

Skills

Verification methodologies

Test bench development

Mentoring junior engineers

Education

Bachelor's degree in EE/CE/CS or equivalent

Tools

UVM

SystemVerilog

Job description

Google's Devices & Services team in Mountain View, CA seeks a Senior Design Verification Engineer to drive verification of digital blocks for custom silicon. You will plan verification strategies, build robust test benches, and mentor junior engineers.

Requirements include a Bachelor's in EE/CE/CS, 5 years in verification with UVM/SystemVerilog, and experience with test benches and environments. Preferred: advanced degrees and ARM/RISC-V verification experience.