Senior Signal Integrity Lead for 112G/224G AI Networking

Upscale; Kentucky; Vor Ort; USD 130.000 - 180.000; Vollzeit

Zusammenfassung

Upscale, Inc. is seeking a Senior Signal Integrity Engineer to lead SI/PI design and validation for high‑speed networking, AI, and data center products. You will own channel budgets and drive pre/post layout analyses for 112G/224G SerDes implementations.

You will mentor juniors, collaborate with silicon, package, board teams, and interface with vendors to resolve complex SI/PI challenges. This is a hands‑on role focused on delivering robust, scalable high‑speed designs.

Qualifikationen

• BS/MS in Electrical Engineering or related field.
• 5+ years of experience in Signal Integrity, High-Speed Design, or related areas.

Aufgaben

• Lead Signal Integrity and Power Integrity analysis for complex PCB and system designs.
• Define SI/PI architecture, design rules, and channel budgets for high-speed interfaces.
• Perform detailed channel simulations and optimization using industry-standard tools.
• Drive correlation between simulation and laboratory measurements.
• Develop and validate models for packages, PCBs, connectors, cables, and complete channels.
• Conduct pre-layout and post-layout SI/PI analysis.
• Perform compliance and interoperability analysis for industry standards.
• Debug complex signal integrity issues and drive root-cause resolution.
• Define PCB stackups, routing requirements, via structures, and return path strategies.
• Mentor junior engineers and provide technical leadership across projects.
• Collaborate with silicon, package, board, mechanical, and manufacturing teams.
• Interface with vendors and customers on SI/PI-related technical topics.

Kenntnisse

Signal Integrity

High-Speed Design

Electromagnetic theory

Transmission line analysis

Ausbildung

Electrical Engineering

Tools

Ansys HFSS

Cadence Clarity

Cadence Sigrity

Keysight ADS

Jobbeschreibung

Upscale, Inc. is seeking a Senior Signal Integrity Engineer to lead SI/PI design and validation for high‑speed networking, AI, and data center products. You will own channel budgets and drive pre/post layout analyses for 112G/224G SerDes implementations.

You will mentor juniors, collaborate with silicon, package, board teams, and interface with vendors to resolve complex SI/PI challenges. This is a hands‑on role focused on delivering robust, scalable high‑speed designs.