Senior SI/PI Engineer — Advanced 2.5D/3D Packaging

Amazon Inc.; Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Job summary

Annapurna Labs, an organization within Amazon, is seeking a Sr. Signal & Power Integrity Engineer to drive SI/PI analysis for next-generation machine learning and data center ASIC packaging.

You will own the package-level SI/PI strategy, from architecture trade-offs to design closure, measurement, and validation. You will collaborate with ASIC, board, and packaging teams to optimize electrical performance and manufacturing yield across 2.5D/3D-IC packaging, while applying advanced EM/IR analysis

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 10+ years of experience in signal integrity and package design.
• Deep expertise in SI/PI analysis: S-parameter extraction, PDN impedance, IR drop, crosstalk, return loss.
• Hands-on with EM simulation tools such as HFSS, Sigrity, ADS, or equivalent.

Responsibilities

• Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and interposers.
• Design and optimize package stack-ups for impedance and power delivery.
• Perform high-speed channel simulations and eye-diagram analysis for die-to-die and die-to-board interfaces.
• Model and optimize PDN impedance from die bumps to board across stacks.
• Collaborate with ASIC, board, and packaging teams to co-optimize electrical performance.
• Develop SI/PI modeling flows, automation scripts, and design guidelines.

Skills

Signal integrity

Power integrity

Package design

EM simulation

S-parameter extraction

PDN analysis

Interconnect modeling

Education

Bachelor's degree in Electrical Engineering

Master's degree (preferred)

Tools

HFSS

Cadence Sigrity PowerSI

Cadence PowerDC

Clarity

ADS

Job description

Annapurna Labs, an organization within Amazon, is seeking a Sr. Signal & Power Integrity Engineer to drive SI/PI analysis for next-generation machine learning and data center ASIC packaging.

You will own the package-level SI/PI strategy, from architecture trade-offs to design closure, measurement, and validation. You will collaborate with ASIC, board, and packaging teams to optimize electrical performance and manufacturing yield across 2.5D/3D-IC packaging, while applying advanced EM/IR analysis