Senior IC Package Layout Engineer - 2.5D/3D-IC

Amazon Inc.; Tempe (AZ); On-site; USD 154,000 - 215,000; Full time

Job summary

Annapurna Labs, within AWS, is seeking a Package Layout Design Engineer to design advanced IC packages for ML and data center ASICs. You will drive layout tasks from floor planning through tape-out, collaborating with senior engineers, SI/PI, thermal, and manufacturing teams to meet performance and reliability goals.

Experience with 2.5D/3D packaging, RDL/substrate routing, and DFM/DRC is essential. Strong communication and tooling skills (Cadence APD/SiP, Synopsys IC Packaging, Mentor

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of IC package layout and physical design experience.
• Hands-on experience with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent
• Exposure to 2.5D/3D-IC packaging, RDL, TSV, and interposer technologies.
• Familiarity with design rules, DFM constraints, and physical verification methodologies (DRC, connectivity).
• Good communication skills and ability to work across design, SI/PI, and manufacturing teams.

Responsibilities

• Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Implement physical designs for 2.5D interposer, 3D‑IC, fan‑out WLP, and silicon bridge interconnects (CoWoS, EMIB).
• Support package floorplan development considering die placement, bump maps, power/ground distribution, signal routing, and decoupling cap placement.
• Perform RDL and substrate routing for high‑density interconnects across multi‑layer substrates or interposers.
• Coordinate with ASIC physical design teams to support die‑level RDL routing and bump planning.
• Contribute to cross‑level layout co‑optimization across die RDL, interposer/substrate, and PCB levels.
• Maintain package stack‑up definitions with SI/PI and materials teams.
• Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
• Follow and refine package design rules with OSAT partners to ensure DFM compliance.
• Collaborate with SI/PI to incorporate impedance control and PDN layout into the physical layout.

Skills

Communication skills

Packaging technologies

ARM DSP ISAs

Impedance control

PDN layout

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical or Communications Engineering

MS with 3+ years in IC package layout and physical design

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Python scripting for automation

Job description

Annapurna Labs, within AWS, is seeking a Package Layout Design Engineer to design advanced IC packages for ML and data center ASICs. You will drive layout tasks from floor planning through tape-out, collaborating with senior engineers, SI/PI, thermal, and manufacturing teams to meet performance and reliability goals.

Experience with 2.5D/3D packaging, RDL/substrate routing, and DFM/DRC is essential. Strong communication and tooling skills (Cadence APD/SiP, Synopsys IC Packaging, Mentor