Senior SI Engineer: High-Speed Interconnects

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 310,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA is seeking a Senior Signal Integrity Engineer to join our Packaging and Systems team. You will lead high-speed SerDes channel design, simulation, and correlation across die, package, board, and connectors to deliver robust interconnects for HPC and AI platforms.

You will work with silicon, package, board, mechanical, and validation teams, drive SI methodologies, and translate measurement findings into reusable design flows, enabling scalable and reliable performance at scale.

Qualifications

• BS, MS, or PhD in Electrical Engineering or equivalent.
• 8+ years in signal integrity or high-speed interconnect design.
• Strong electromagnetics, transmission line, and NRZ/PAM4 knowledge.
• Experience with SerDes design for packaging and system applications.
• Hands-on with SI tools: HFSS, SIwave, Cadence Sigrity, ADS, HSPICE.

Responsibilities

• Lead SI design and analysis for high-speed SerDes channels across die, package, board, connector.
• Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with focus on channel loss, discontinuities, return path behavior, and crosstalk.
• Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems.
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures.
• Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met.
• Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and signoff confidence.
• Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co-optimize electrical performance across the full product stack.
• Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs.

Skills

High-speed SerDes design

Signal integrity analysis

Channel modeling

S-parameter / IBIS-AMI flows

Lab measurement correlation

Education

BS/MS/PhD in Electrical Engineering

Tools

Ansys HFSS

SIwave

Cadence Sigrity

ADS

HSPICE

Job description

NVIDIA is seeking a Senior Signal Integrity Engineer to join our Packaging and Systems team. You will lead high-speed SerDes channel design, simulation, and correlation across die, package, board, and connectors to deliver robust interconnects for HPC and AI platforms.

You will work with silicon, package, board, mechanical, and validation teams, drive SI methodologies, and translate measurement findings into reusable design flows, enabling scalable and reliable performance at scale.