Senior Signal Integrity Engineer - 2.5D/3D Packaging Lead

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 168,000 - 310,500; Full time

Benefits offered by this job

Equity and comprehensive benefits package

Job summary

NVIDIA Gruppe is seeking a Senior Signal Integrity Engineer for its Packaging and Systems team in Santa Clara, California. The ideal candidate will lead high-speed SerDes channel design and signal integrity analysis.

This role requires a strong background in electromagnetics and hands-on experience with standard SI tools. The competitive salary ranges from $168,000 to $264,500 based on experience and level.

Qualifications

• 8+ years of industry experience in signal integrity or related hardware development roles.
• Strong understanding of NRZ and PAM4 signaling and end-to-end channel budgets.
• Experience with simulation-to-measurement correlation and lab-based model validation.

Responsibilities

• Lead signal integrity design and analysis for high-speed SerDes channels.
• Develop simulation flows for advanced packaging technologies.
• Automate analysis and improve SI methodology across programs.

Skills

Signal integrity design

Electromagnetics

High-speed interconnect design

Channel modeling

Hands-on experience with SI tools

Education

BS, MS, or PhD in Electrical Engineering

Tools

Ansys HFSS

Cadence Sigrity

HSPICE

Job description

NVIDIA Gruppe is seeking a Senior Signal Integrity Engineer for its Packaging and Systems team in Santa Clara, California. The ideal candidate will lead high-speed SerDes channel design and signal integrity analysis.

This role requires a strong background in electromagnetics and hands-on experience with standard SI tools. The competitive salary ranges from $168,000 to $264,500 based on experience and level.