Senior Signal Integrity Engineer – LPU Packaging

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 310,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA is seeking a Senior Signal Integrity Engineer to join our Packaging and Systems team. You will lead high-speed SerDes channel design, simulation, and correlation across die, package, board, and connectors to deliver robust interconnects for HPC and AI platforms.

You will work with silicon, package, board, mechanical, and validation teams, drive SI methodologies, and translate measurement findings into reusable design flows, enabling scalable and reliable performance at scale.

Qualifications

• BS, MS, or PhD in Electrical Engineering or equivalent.
• 8+ years in signal integrity or high-speed interconnect design.
• Strong electromagnetics, transmission line, and NRZ/PAM4 knowledge.
• Experience with SerDes design for packaging and system applications.
• Hands-on with SI tools: HFSS, SIwave, Cadence Sigrity, ADS, HSPICE.

Responsibilities

• Lead SI design and analysis for high-speed SerDes channels across die, package, board, connector.
• Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with focus on channel loss, discontinuities, return path behavior, and crosstalk.
• Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems.
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures.
• Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met.
• Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and signoff confidence.
• Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co-optimize electrical performance across the full product stack.
• Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs.

Skills

High-speed SerDes design

Signal integrity analysis

Channel modeling

S-parameter / IBIS-AMI flows

Lab measurement correlation

Education

BS/MS/PhD in Electrical Engineering

Tools

Ansys HFSS

SIwave

Cadence Sigrity

ADS

HSPICE

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. We have built an incredible legacy of innovation fueled by great technology and amazing people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will be immersed in a diverse, supportive environment where everyone is inspired to do their life’s work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is now looking for a Senior Signal Integrity Engineer to join our Packaging and Systems team! In this role, you will drive high-speed SerDes channel design, simulation, and correlation for next-generation advanced packages and data center platforms. You will work across silicon, package, board, and system boundaries to develop robust high-speed interconnect solutions for demanding HPC and AI applications, where signal integrity is critical to performance, scale, and reliability!

What you’ll be doing

• Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces
• Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with strong focus on channel loss, discontinuities, return path behavior, and crosstalk
• Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures
• Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met
• Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and signoff confidence
• Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co-optimize electrical performance across the full product stack
• Support interface bring-up, debug, and margin analysis, and help translate correlation learnings into improved design methods and reusable flows
• Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs

What we need to see

• BS, MS, or PhD in Electrical Engineering or equivalent experience
• 8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles
• Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior
• Proven experience with high-speed SerDes design and analysis for advanced packaging and/or large-scale system applications
• Hands-on experience with industry-standard SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent
• Experience building and using channel models, S-parameters, IBIS-AMI based flows, and time/frequency-domain analysis techniques
• Strong understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets
• Experience with simulation-to-measurement correlation and lab-based model validation using VNA, TDR, and high-speed scope measurements
• Ability to work effectively across cross-functional teams and drive technical decisions in a fast-moving product environment

Ways to stand out from the crowd

• Experience with package and system SI for PCIe, CXL, NVLink, Ethernet, or other high-speed compute and networking interfaces
• Deep knowledge of advanced packaging structures, substrate technologies, and chip-package-board co-design
• Background in SI design for data center, AI infrastructure, or HPC platforms
• Experience improving SI signoff methodology, building reusable automation flows, or driving design rule development
• Familiarity with mixed-domain tradeoffs across SI, PI, thermal, mechanical, and manufacturability considerations

We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 6, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.