Senior SerDes Design & Validation Engineer - High-Speed IP

Apple, Inc.; Beaverton (OR); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. seeks a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP. You will design, integrate and validate analog and mixed-signal blocks, develop test plans, and work with production test teams to ensure silicon quality.

The role emphasizes collaboration across design and validation teams, driving robust IP from bring-up to production in a fast-paced environment. Applicants should have a BS and 10+ years of relevant experience, deep knowledge of SerDes

Qualifications

• BS degree and 10+ years of relevant industry experience.

Responsibilities

• Ownership of SerDes system bring-up, validation and debug in system environment.
• Define DFT needs to enhance testability and silicon success.
• Work with design teams to understand architecture and verify SerDes operation with higher level control logic.

Skills

Analog mixed-signal design

SerDes high-speed links

DFT for testability

Lab/production testing

AMS IP development

Scripting/automation

PCIe/USB/DP/MPHY

CDR architectures

CTLE/DFE

AI/ML for silicon

Education

Bachelor's degree (BS)

Job description

Apple Inc. seeks a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP. You will design, integrate and validate analog and mixed-signal blocks, develop test plans, and work with production test teams to ensure silicon quality.

The role emphasizes collaboration across design and validation teams, driving robust IP from bring-up to production in a fast-paced environment. Applicants should have a BS and 10+ years of relevant experience, deep knowledge of SerDes