Senior SerDes Design & Validation Engineer

Apple Inc.; Austin (TX); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. is seeking a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP.

You will drive the design, integration and validation of analog and mixed-signal blocks for SerDes PHY applications, optimizing power, performance and area while ensuring testability and robust silicon bring-up. In this role you will own SerDes bring-up, validate operation in system environments, define DFT needs, and collaborate with design teams and production test to debug complex

Qualifications

• Bachelor's degree required.
• Experience in high-speed SerDes and mixed-signal design preferred.
• Experience with lab/test automation and data analysis preferred.

Responsibilities

• Own SerDes system bring-up, validation and debug in system environments.
• Collaborate with design teams to define DFT needs for testability and first-silicon success.
• Contribute to mixed-signal verification to understand SerDes operation and interaction with control logic.
• Develop test plans and analyze data to ensure robust IP design.

Skills

High-speed links

Analog mixed-signal design

DFT and testability

Lab testing & debug

Scripting & automation

AMS IP development

PCIe/USB/DP/MPHY knowledge

CDR architectures

Education

Bachelor's degree

Tools

Cadence

Job description

Apple Inc. is seeking a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP.

You will drive the design, integration and validation of analog and mixed-signal blocks for SerDes PHY applications, optimizing power, performance and area while ensuring testability and robust silicon bring-up. In this role you will own SerDes bring-up, validate operation in system environments, define DFT needs, and collaborate with design teams and production test to debug complex