SerDes Design & Validation Lead

Apple Inc.; Beaverton (OR); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. seeks a SerDes Design and Validation Engineer to lead system validation for high-performance SerDes IP. You will design and validate analog/mixed-signal blocks, develop test plans, and drive production test readiness.

You’ll work with design, test, and validation teams to ensure robust IP delivery. The ideal candidate brings hands-on lab experience, strong signal integrity understanding, and a passion for solving complex challenges in a collaborative environment.

Qualifications

• Bachelor's degree required.
• Experience in high-speed serial links and SerDes protocols (PCIe, USB, DP, MPHY).
• Design and validation of analog mixed-signal blocks (Bandgap, biasing, LDOs, amplifiers, DACs/ADCs).
• Familiarity with DFT techniques for PHY validation.
• Hands-on lab and production testing, debug, data analysis.

Responsibilities

• Ownership of SerDes system bring-up, validation and debug in system environments.
• Collaborate with design teams to define DFT needs for testability and silicon success.
• Involvement in mixed-signal verification to understand SerDes operation and interaction with control logic.

Skills

SerDes design

Analog mixed-signal design

DFT for analog

Lab testing & debugging

Data analysis

Scripting/automation

Cross-functional collaboration

Education

Bachelor's degree

Tools

Python scripting

Job description

Apple Inc. seeks a SerDes Design and Validation Engineer to lead system validation for high-performance SerDes IP. You will design and validate analog/mixed-signal blocks, develop test plans, and drive production test readiness.

You’ll work with design, test, and validation teams to ensure robust IP delivery. The ideal candidate brings hands-on lab experience, strong signal integrity understanding, and a passion for solving complex challenges in a collaborative environment.