Senior SerDes Clocking Architect - Ultra-Low Jitter PLLs

Upscale, Inc.; United States; On-site; USD 313,000 - 353,000; Full time

Job summary

Upscale, Inc. is building a world-class SerDes clocking organization to enable ultra-high-speed AI data-center connectivity.

We seek a senior technical leader to define the clocking architecture, drive PLL innovations, and collaborate across analog, mixed-signal, digital, layout, and silicon validation teams for exceptional timing performance at 5nm and below. You will establish clocking architecture, tackle jitter and power-efficiency challenges, design end-to-end clocking paths, and lead

Qualifications

• MS or PhD in Electrical Engineering or related field with focus on analog/mixed-signal IC design.
• Proven track record delivering ultra-low-jitter PLLs (100 fs-class RMS) in 5nm or below.
• Deep PLL architecture knowledge: phase detectors, charge pumps, loop filters, oscillators, dividers.
• Strong understanding of phase noise, jitter, reference spurs, and clock quality impact on SerDes.
• Ability to translate timing requirements into circuit specifications and architectures.
• Experience with clock distribution design and managing coupling, skew, power integrity.
• Hands-on experience with EM simulation/extraction tools.
• Experience developing SystemVerilog-based models and verification environments for PLLs.

Responsibilities

• Define end-to-end clocking architecture for next-generation SerDes.
• Lead ultra-low-jitter PLL design targeting <100 fs RMS jitter.
• Evaluate hybrid and digital PLL architectures and trade-offs.
• Develop solutions to mitigate PLL coupling and clock-generation interference.
• Define comprehensive clock distribution with resonant techniques for power efficiency.
• Use EM tools to optimize inductors, networks, and interconnects.
• Create SystemVerilog models for verification and system integration.
• Collaborate with SerDes TX/RX, ADC, AMS, and silicon teams to optimize link performance.
• Drive silicon characterization, jitter analysis, and silicon-to-model correlation.

Skills

Clocking architecture

PLL design

SerDes expertise

EM analysis

SystemVerilog models

Low-jitter PLLs

High-frequency design

Clock distribution

Power efficiency

Education

MS or PhD in Electrical Engineering

Advanced CMOS process knowledge

Tools

Cadence EMX

Ansys HFSS

Job description

Upscale, Inc. is building a world-class SerDes clocking organization to enable ultra-high-speed AI data-center connectivity.

We seek a senior technical leader to define the clocking architecture, drive PLL innovations, and collaborate across analog, mixed-signal, digital, layout, and silicon validation teams for exceptional timing performance at 5nm and below. You will establish clocking architecture, tackle jitter and power-efficiency challenges, design end-to-end clocking paths, and lead