Senior SerDes & ADC Architect (5nm, 100+ GS/s)

Upscale, Inc.; United States; On-site; USD 335,000 - 388,000; Full time

Job summary

Upscale, Inc. in the United States is building a world-class SerDes engineering organization focused on ultra-high-speed connectivity for AI data centers and HPC.

We seek a technical leader to define and drive the architecture and implementation of next-generation SerDes receivers, ADCs, and analog front-end blocks in 5nm and below. You will shape receiver architecture, lead critical design trades, mentor engineers, and collaborate with DSP, clocking, packaging, and silicon validation teams to

Qualifications

• MS or PhD in Electrical Engineering or related field.
• Extensive experience in high-speed analog and mixed-signal IC design.
• Expertise in SerDes receiver architectures and ADC-based receivers.
• Experience with 5nm or below process technologies.
• Strong architecture-level decision making supported by circuit-level analysis.

Responsibilities

• Define and drive the architecture of next-generation SerDes receivers.
• Lead ADC development targeting 100+ GS/s and high sampling rate.
• Drive high-bandwidth analog front-end design and equalization.
• Lead implementation in 5nm and below technologies.
• Collaborate across analog, DSP, clocking, digital, and silicon validation.

Skills

High-speed analog design

SerDes receiver architecture

CMOS circuit design (5nm and below)

Education

MS or PhD in Electrical Engineering

Job description

Upscale, Inc. in the United States is building a world-class SerDes engineering organization focused on ultra-high-speed connectivity for AI data centers and HPC.

We seek a technical leader to define and drive the architecture and implementation of next-generation SerDes receivers, ADCs, and analog front-end blocks in 5nm and below. You will shape receiver architecture, lead critical design trades, mentor engineers, and collaborate with DSP, clocking, packaging, and silicon validation teams to