Distinguished Engineer, SerDes Clocking

Upscale, Inc.; United States; On-site; USD 313,000 - 353,000; Full time

Job summary

Upscale, Inc. is building a world-class SerDes clocking organization to enable ultra-high-speed AI data-center connectivity.

We seek a senior technical leader to define the clocking architecture, drive PLL innovations, and collaborate across analog, mixed-signal, digital, layout, and silicon validation teams for exceptional timing performance at 5nm and below. You will establish clocking architecture, tackle jitter and power-efficiency challenges, design end-to-end clocking paths, and lead

Qualifications

• MS or PhD in Electrical Engineering or related field with focus on analog/mixed-signal IC design.
• Proven track record delivering ultra-low-jitter PLLs (100 fs-class RMS) in 5nm or below.
• Deep PLL architecture knowledge: phase detectors, charge pumps, loop filters, oscillators, dividers.
• Strong understanding of phase noise, jitter, reference spurs, and clock quality impact on SerDes.
• Ability to translate timing requirements into circuit specifications and architectures.
• Experience with clock distribution design and managing coupling, skew, power integrity.
• Hands-on experience with EM simulation/extraction tools.
• Experience developing SystemVerilog-based models and verification environments for PLLs.

Responsibilities

• Define end-to-end clocking architecture for next-generation SerDes.
• Lead ultra-low-jitter PLL design targeting <100 fs RMS jitter.
• Evaluate hybrid and digital PLL architectures and trade-offs.
• Develop solutions to mitigate PLL coupling and clock-generation interference.
• Define comprehensive clock distribution with resonant techniques for power efficiency.
• Use EM tools to optimize inductors, networks, and interconnects.
• Create SystemVerilog models for verification and system integration.
• Collaborate with SerDes TX/RX, ADC, AMS, and silicon teams to optimize link performance.
• Drive silicon characterization, jitter analysis, and silicon-to-model correlation.

Skills

Clocking architecture

PLL design

SerDes expertise

EM analysis

SystemVerilog models

Low-jitter PLLs

High-frequency design

Clock distribution

Power efficiency

Education

MS or PhD in Electrical Engineering

Advanced CMOS process knowledge

Tools

Cadence EMX

Ansys HFSS

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

We are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.

We are seeking an exceptional technical leader to define the clocking architecture for next-generation SerDes, spanning ultra-low-jitter phase-locked loops (PLLs) and high-performance clock distribution networks.

This is a senior individual contributor role for a recognized expert in high-speed clocking technology who can drive architectural innovation, lead critical circuit development, and solve some of the most challenging jitter, coupling, and power-efficiency problems in advanced CMOS.

You will establish the clocking architecture and design methodology for our next-generation SerDes platform, working across analog, mixed-signal, digital, layout, and system teams to deliver exceptional timing performance in advanced process technologies at 5nm and below.

Responsibilities:

• Clocking Architecture: Define and drive the end-to-end clocking architecture for next-generation SerDes, including PLLs, clock generation, multiphase clocking, clock distribution, and integration with transmitter and receiver subsystems.
• Ultra-Low-Jitter PLL Design: Lead the architecture and development of ultra-low-jitter PLLs targeting less than 100 fs RMS integrated jitter in advanced CMOS technologies at 5nm and below, meeting stringent system-level timing and noise requirements.
• PLL Architecture Innovation: Evaluate and develop hybrid, digital, and other advanced PLL architectures, making informed trade-offs among jitter, power, area, tuning range, robustness, and implementation complexity.
• Multi-PLL Coupling Management: Develop architectural and circuit-level solutions to mitigate coupling among multiple PLLs and clock-generation blocks, including supply coupling, substrate noise, electromagnetic interactions, reference spurs, and clock-to-clock interference.
• Power-Efficient Clock Distribution: Define and implement advanced clock distribution architectures, including resonant clocking techniques, to reduce clocking power while maintaining stringent jitter, skew, phase-noise, and timing requirements.
• EM Analysis and Optimization: Use electromagnetic simulation and extraction tools to analyze and optimize inductors, resonant networks, clock distribution structures, coupling paths, and high-frequency interconnects.
• Modeling and Verification: Develop SystemVerilog-based behavioral models, verification environments, and architectural models for PLLs and clocking subsystems to enable early system integration, design exploration, and verification of key performance requirements.
• Cross-Functional Technical Leadership: Partner with SerDes TX, RX, ADC, digital, AMS layout, package, and silicon validation teams to optimize overall link performance and ensure clocking architecture decisions align with system requirements.
• Silicon Execution and Correlation: Drive design reviews, implementation strategy, silicon characterization, jitter and phase-noise analysis, and simulation-to-silicon correlation.

Qualifications:

• MS or PhD in Electrical Engineering or a related field, with extensive experience in high-performance analog and mixed-signal IC design.
• Demonstrated success designing and delivering ultra-low-jitter PLLs (100 fs-class RMS integrated jitter) in advanced CMOS technologies at 5nm or below.
• Deep expertise in PLL architecture and circuit design, including phase detectors or phase-frequency detectors, charge pumps where applicable, loop filters, oscillators, frequency dividers, and loop dynamics.
• Strong understanding of phase noise, integrated jitter, reference spurs, loop stability, supply-induced jitter, and the impact of clock quality on high-speed SerDes performance.
• Proven ability to define clocking architectures and translate stringent system-level jitter requirements into circuit-level specifications and implementation strategies.
• Experience with clock distribution design and the management of coupling, skew, power integrity, and electromagnetic interactions.
• Hands-on experience with electromagnetic simulation and extraction tools for analyzing high-frequency circuits and passive structures.
• Experience developing SystemVerilog-based behavioral models and verification environments for PLLs or other mixed-signal clocking systems.
• A strong track record of technical leadership, architectural decision-making, and successful silicon delivery.

• Direct experience developing clocking solutions for 100G+ per-lane SerDes.
• Experience with hybrid PLL architectures, digital PLLs, digitally assisted analog PLLs, or other advanced clock-generation techniques.
• Demonstrated expertise in resonant clock distribution, including resonant network design, energy recovery, clock power optimization, and associated implementation trade-offs.
• Experience managing interference among multiple high-performance PLLs operating within a shared die, including reference distribution, supply isolation, substrate coupling, and electromagnetic coupling.
• Proficiency with tools such as Cadence EMX, Ansys HFSS, or equivalent electromagnetic solvers.
• Experience with advanced-node physical implementation, custom layout, parasitic extraction, and silicon debug.
• Recognized technical contributions through successful silicon products, patents, publications, or industry-leading clocking innovations.

$313,000 - $353,000 a year

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.