Senior SerDes & ADC Architect — 100+ GS/s

Upscale AI, Inc.; United States; On-site; USD 180,000 - 260,000; Full time

Job summary

Upscale, Inc. is building world-class SerDes and high-speed data path technology for AI data centers. The role leads architecture, ADC design, and analog front-end development to deliver ultra-high sampling rates at advanced process nodes.

You will mentor engineers and influence silicon validation and DSP integration across teams. Applicants should possess senior-level expertise in high-speed analog/mixed-signal design, with a track record from architecture through tape-out.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• Expertise in high-speed SerDes receiver architecture.
• Experience with 5nm or below process technologies.
• Strong understanding of high-speed ADC architectures.
• Proven leadership in analog/mixed-signal design.

Responsibilities

• Define and drive architecture of ultra-high-speed SerDes receivers.
• Lead ADC development targeting 100+ GS/s.
• Drive analog front-end and sampling networks.
• Lead 5nm+ design implementations.
• Collaborate with cross-functional teams to deliver SerDes solution.
• Shape technology roadmap and validation.

Skills

High-speed analog design

Mixed-signal IC design

SerDes architecture

ADC architectures

5nm process

Clocking design

DSP integration

Silicon validation

Technical leadership

Cross-functional collaboration

Education

MS/PhD in Electrical Engineering

Job description

Upscale, Inc. is building world-class SerDes and high-speed data path technology for AI data centers. The role leads architecture, ADC design, and analog front-end development to deliver ultra-high sampling rates at advanced process nodes.

You will mentor engineers and influence silicon validation and DSP integration across teams. Applicants should possess senior-level expertise in high-speed analog/mixed-signal design, with a track record from architecture through tape-out.