Senior Serdes & Analog Design Engineer

Samsung Semiconductor; San Jose (CA); On-site; USD 156,000 - 253,000; Full time

Benefits offered by this job

4+ weeks paid time off

Medical/Dental/Vision/401k

Charitable giving match

Fertility/adoption stipend

Onsite gym & wellness

Job summary

Samsung Semiconductor is seeking an experienced engineer to work on architecture and circuits for high-speed Serdes interconnects at the San Jose site. You’ll contribute to Serdes IPs, clock generation, and analog circuits with cutting-edge process technologies.

The role requires deep expertise in RF/Analog/Serdes design, proficiency with Cadence tools, and hands-on layout supervision, with a focus on power and performance in silicon.

Qualifications

• Bachelors with 10+ years, Masters with 8+ years or PhDs with 5+ years of experience.
• Minimum 2+ yrs experience RF/Analog/Serdes SoC design experience.
• Knowledge of analog/mixed-signal circuits (bandgap, LDO, filters).
• Knowledge of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.

Responsibilities

• Design low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologies.
• Translate component design specification to schematics and build simulation test-benches to evaluate performance, power, and reliability.
• Supervise layout designers to generate LVS/DRC clean layouts and optimize for power and performance.
• Validate functionality and performance in Silicon.

Skills

RF/Analog/Serdes

High-speed interconnect

EDA tools

Python scripting

Matlab

Layout supervision

Education

Bachelor's degree (10+ years)

Master's degree (8+ years)

PhD (5+ years)

Tools

Cadence

Spectre

Totem

EMX

Job description

Samsung Semiconductor is seeking an experienced engineer to work on architecture and circuits for high-speed Serdes interconnects at the San Jose site. You’ll contribute to Serdes IPs, clock generation, and analog circuits with cutting-edge process technologies.

The role requires deep expertise in RF/Analog/Serdes design, proficiency with Cadence tools, and hands-on layout supervision, with a focus on power and performance in silicon.