Senior Manager: Serdes Analog Design & Silicon Validation

Samsung Semiconductor; San Jose (CA); Sur place; USD 219 000 - 351 000; Plein temps

Avantages offerts par ce poste

Medical/Dental/Vision

401(k)

Paid time off

Fertility care stipend

Wellness programs

Résumé du poste

Samsung Semiconductor is seeking a Senior Manager for Serdes Analog Design in our onsite San Jose office. You will define architecture, supervise designers, and drive silicon validation across serdes projects.

The role demands deep analog/mixed-signal expertise, strong leadership, and hands-on design and scripting capabilities. A robust benefits package and a focus on innovation support a flexible, collaborative environment.

Qualifications

• Minimum 7+ years in Analog/Serdes SoC design.
• Experience with bandgap, LDO, filters.
• Knowledge of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.

Responsabilités

• Define architecture and circuits for serdes projects.
• Supervise designers to complete the project and conduct silicon validation.
• Translate component design specification to schematics.
• Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.
• Supervise layout of the complete project.
• Optimize layout to improve the power consumption and performance of circuits.

Connaissances

High-speed Serdes

Analog design

Circuit design

EDA scripting

Formation

Bachelor's degree in EE

Master's degree in EE

PhD in related field

Outils

Cadence

Spectre

Totem

EMX

Description du poste

Samsung Semiconductor is seeking a Senior Manager for Serdes Analog Design in our onsite San Jose office. You will define architecture, supervise designers, and drive silicon validation across serdes projects.

The role demands deep analog/mixed-signal expertise, strong leadership, and hands-on design and scripting capabilities. A robust benefits package and a focus on innovation support a flexible, collaborative environment.