Senior Analog IC Design Engineer — SerDes & High-Speed I/O

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 119,000 - 221,000; Full time

Job summary

Cadence Design Systems, Inc. in San Jose, California, is seeking a Lead Analog IC Design Engineer to drive the development of analog and mixed-signal circuits from concept to verification, ensuring customer specifications are met.

The role requires expertise in CMOS SerDes, high-speed I/O, and strong knowledge of jitter and signal integrity, with collaboration across functional teams to deliver robust designs.

Qualifications

• At least three years of experience designing CMOS SerDes or high-speed I/O ICs.
• Experience with SerDes blocks: transmitters/receivers, serializers/deserializers, phase interpolators, PLLs, high-speed clocks, bias circuits, regulators.
• Strong understanding of jitter and signal-equalization techniques.
• Proficiency with CAD tools for circuit simulation, layout, and physical verification.
• Master’s degree or Ph.D. in electrical engineering.
• Strong problem-solving and analog design aptitude.
• Clear written and verbal communication and teamwork.

Responsibilities

• Lead analog IC design from concept to verification to meet customer requirements.
• Collaborate with cross-functional teams to translate specifications into robust circuits.
• Mentor junior designers and lead design reviews.

Skills

CMOS SerDes

Analog layout

Signal integrity

CAD tools

Team collaboration

Communication skills

Education

Master’s or PhD EE

Tools

Cadence tools

Lab testing

Job description

Cadence Design Systems, Inc. in San Jose, California, is seeking a Lead Analog IC Design Engineer to drive the development of analog and mixed-signal circuits from concept to verification, ensuring customer specifications are met.

The role requires expertise in CMOS SerDes, high-speed I/O, and strong knowledge of jitter and signal integrity, with collaboration across functional teams to deliver robust designs.