Principal Engineer, Serdes Analog Design

Samsung Semiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

Medical/Dental/Vision

401(k)

Paid time off

Fertility care stipend

Wellness programs

Job summary

Samsung Semiconductor is seeking a Senior Manager for Serdes Analog Design in our onsite San Jose office. You will define architecture, supervise designers, and drive silicon validation across serdes projects.

The role demands deep analog/mixed-signal expertise, strong leadership, and hands-on design and scripting capabilities. A robust benefits package and a focus on innovation support a flexible, collaborative environment.

Qualifications

• Minimum 7+ years in Analog/Serdes SoC design.
• Experience with bandgap, LDO, filters.
• Knowledge of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.

Responsibilities

• Define architecture and circuits for serdes projects.
• Supervise designers to complete the project and conduct silicon validation.
• Translate component design specification to schematics.
• Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.
• Supervise layout of the complete project.
• Optimize layout to improve the power consumption and performance of circuits.

Skills

High-speed Serdes

Analog design

Circuit design

EDA scripting

Education

Bachelor's degree in EE

Master's degree in EE

PhD in related field

Tools

Cadence

Spectre

Totem

EMX

Job description

Senior Manager, Serdes Analog Design

Location: Onsite at our San Jose office, 5 days a week.

What You’ll Do

• Define architecture and circuits for serdes projects.
• Supervise designers to complete the project and conduct silicon validation.
• Translate component design specification to schematics.
• Build simulation test‑benches to evaluate circuit performance, functionality, power consumption and reliability.
• Supervise layout of the complete project.
• Optimize layout to improve the power consumption and performance of circuits.

What You Bring

• Bachelors with 20+ years, Masters with 18+ years or PhDs with 15+ years of experience.
• Minimum 7+ years experience in Analog/Serdes SoC design.
• Knowledge and experience with analog circuits/mixed signal circuits such as bandgap, LDO, filters.
• Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
• Knowledge of Serdes architecture and high‑speed interconnect standards (USB, PCIe, UCIe).
• Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.
• Well‑versed in EDA tools (Cadence, Spectre, Totem, EMX).
• Comfortable with scripting languages (Python, Matlab).
• Inclusive, collaborative, innovative, and resilient.

What We Offer

• Pay range $219,000—$351,000 USD (US locations).
• Incentive opportunities reward employees based on individual and company performance.
• Benefits centered on well‑being: Medical/Dental/Vision, 401(k), inclusive rewards plan.
• Generous paid time off: 4+ weeks per year, holidays, sick leave.
• Family support: fertility care stipend, adoption support, medical travel, virtual vet care.
• Emotional wellness: on-demand apps and confidential therapy sessions.
• Fitness: onsite café and gym, virtual classes.
• Flexible environment to balance work and life.

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.