Senior PLL & Analog Designer (RF/Serdes)

Samsung Semiconductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

4+ weeks PTO

Medical/Dental/Vision/401k

Charitable giving match

Job summary

Samsung Semiconductor Inc. in San Jose, CA, is seeking a Senior/Staff PLL Designer to develop high-performance PLLs and clocking subsystems for RF transceivers and high-speed I/O in deep-submicron CMOS.

You will collaborate with digital and software teams, perform system modeling, verification, and production support, and contribute to layout and lab testing to meet stringent requirements.

Qualifications

• Bachelor’s with 10+ years of experience in a related field.
• Master’s with 8+ years of experience, or PhD with 5 years of experience.

Responsibilities

• Design RF/Analog PLL and clocking circuits using advanced deep-submicron CMOS technologies.
• Design Serdes analog PHY circuits using advanced deep-submicron CMOS technologies.
• Perform system modeling and analysis for mixed signal system.
• Perform design verification and production support tasks.
• Work closely with digital and software developers to meet system requirements.

Skills

PLL design

Problem solving

Communication skills

Analytical skills

Lab testing

Education

Bachelor’s degree in related field

Master’s degree in related field

PhD in related field

Tools

Spectre

SpectreRF

AMS simulator

Matlab

Job description

Samsung Semiconductor Inc. in San Jose, CA, is seeking a Senior/Staff PLL Designer to develop high-performance PLLs and clocking subsystems for RF transceivers and high-speed I/O in deep-submicron CMOS.

You will collaborate with digital and software teams, perform system modeling, verification, and production support, and contribute to layout and lab testing to meet stringent requirements.