ASIC RTL Design Engineer: High-Performance SoCs & RISC-V

Xcelerium; Irvine (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

Xcelerium, located in Irvine, CA, is seeking an ASIC RTL Design Engineer to develop high-performance, low-power digital designs and RISC-V cores. You will collaborate with various teams to optimize designs, ensuring quality and efficiency.

This role requires a Bachelor's degree in engineering and over 5 years of experience. A strong understanding of Verilog/SystemVerilog and a passion for technology will be essential for success in this innovative environment.

Qualifications

• 5+ years of relevant professional experience in ASIC design.
• Familiarity with RTL to GDS design flow.
• Passion for learning new technologies.

Responsibilities

• Architect, design, and implement digital designs for ASICs and SoCs.
• Microarchitecture development and specification with collaborative documentation.
• Optimize physical design to meet frequency, area, and power goals.

Skills

Logic design using Verilog/SystemVerilog

Processor architecture knowledge

Strong programming skills in Python, C/C++, or assembly

Education

Bachelor's in Computer Engineering or Electrical Engineering

Job description

Xcelerium, located in Irvine, CA, is seeking an ASIC RTL Design Engineer to develop high-performance, low-power digital designs and RISC-V cores. You will collaborate with various teams to optimize designs, ensuring quality and efficiency.

This role requires a Bachelor's degree in engineering and over 5 years of experience. A strong understanding of Verilog/SystemVerilog and a passion for technology will be essential for success in this innovative environment.