Senior RTL Engineer – AI-Enhanced Verification

Microchip Technology Inc.; Chandler (AZ); On-site; USD 110,000 - 150,000; Full time

Job summary

Microchip Technology Inc is seeking a Senior Engineer I – design to join our team in Chandler, AZ. The role focuses on RTL design (Verilog/SystemVerilog), functional verification, and contributing to next‑generation mixed‑signal and digital products.

AI/ML‑assisted design methodologies and software skills will enhance productivity and verification quality. The ideal candidate brings strong hardware design fundamentals, 5+ years of experience, and hands-on experience with industry EDA tools.

Qualifications

• BSEE with microelectronics emphasis required.
• 5 years of experience required.
• Proficiency in Verilog/SystemVerilog for RTL design.
• Experience with UVM-based verification environments.
• Understanding of digital design fundamentals: timing, synthesis constraints, clock domain crossings.
• Programming in Python; familiarity with TCL or shell scripting.
• Experience with industry EDA tools (Synopsys, Cadence, or Siemens).
• Masters in Electrical Engineering preferred.

Responsibilities

• Design, code, and optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC implementation.
• Develop and execute verification plans using UVM/SystemVerilog-based testbenches.
• Write constrained-random and directed tests to achieve functional and code coverage targets.
• Apply AI/ML techniques to improve verification closure, coverage analysis, regression optimization, and bug triaging.
• Develop scripts and automation tools (Python, TCL) to streamline design and verification workflows.
• Collaborate with architecture, analog, physical design, and software teams to ensure design correctness and integration.
• Perform lint, CDC, and synthesis checks; resolve issues through the design cycle.
• Participate in design reviews, specification development, and documentation.

Skills

Verilog

SystemVerilog

Python

UVM-based verification

Design verification

Education

BSEE with course emphasis on microelectronics

Master's in Electrical Engineering

Tools

TCL

Shell scripting

EDA tools (Synopsys/Cadence/Siemens)

Job description

Microchip Technology Inc is seeking a Senior Engineer I – design to join our team in Chandler, AZ. The role focuses on RTL design (Verilog/SystemVerilog), functional verification, and contributing to next‑generation mixed‑signal and digital products.

AI/ML‑assisted design methodologies and software skills will enhance productivity and verification quality. The ideal candidate brings strong hardware design fundamentals, 5+ years of experience, and hands-on experience with industry EDA tools.