Senior Verification Engineer - SoC/FPGA & AI-Driven Tools

Microchip Technology Inc.; Chandler (AZ); Hybride; USD 91 000 - 232 000; Plein temps

Résumé du poste

Microchip Technology Inc in Chandler, AZ is seeking an experienced Verification Engineer for our FPGA/SoC focus. You will work on verification of next‑generation, secure, low‑power FPGA device products, employing constrained random, formal, and C based verification methods.

You will develop reusable UVM testbenches, contribute to RTL and gate-level verification, and collaborate with architecture, design, emulation, and hardware prototyping teams to ensure first-silicon success.

Qualifications

• 12.5+ years in functional verification of complex SoC designs.
• Expertise in SystemVerilog, UVM, formal verification methodologies.
• Proven experience in methodology development and tool automation.

Responsabilités

• Verify complex subsystems and SoCs using constrained random, formal, and C-based methods.
• Develop and maintain reusable UVM testbenches and environments.
• Involve in RTL, power-aware and gate-level verification.
• Apply AI/ML-enabled verification methodologies to improve quality and productivity.
• Collaborate with emulation and hardware prototyping teams to unify verification.
• Mentor junior team members and collaborate with architecture and design teams.

Connaissances

SystemVerilog

UVM

Formal verification

Python

C/C++

SoC verification

ARM/RISC-V

AI/ML tools

Git

Formation

BS in Electrical/Electronic Engineering

MS in Electrical Engineering (preferred)

Outils

Siemens Cadence

Synopsys verification suites

EDA tools scripting

Description du poste

Microchip Technology Inc in Chandler, AZ is seeking an experienced Verification Engineer for our FPGA/SoC focus. You will work on verification of next‑generation, secure, low‑power FPGA device products, employing constrained random, formal, and C based verification methods.

You will develop reusable UVM testbenches, contribute to RTL and gate-level verification, and collaborate with architecture, design, emulation, and hardware prototyping teams to ensure first-silicon success.