Senior Verification Engineer - SoC/FPGA AI-Driven

Microchip Technology Inc; Chandler (AZ); On-site; USD 91,000 - 232,000; Full time

Job summary

Microchip Technology Inc in Chandler, AZ is seeking an experienced verification engineer to verify next‑generation, highly secure, low‑power FPGA device products. The role emphasizes constrained random and formal verification, reusable UVM environments, and collaboration with architecture and design teams.

You will work across RTL, power-aware, and post-silicon debug, leveraging AI/ML-driven verification and cross‑functional teams. Mentoring junior engineers is part of the responsibilities.

Qualifications

• 12+ years in functional verification of complex SoC designs.
• Expertise in SystemVerilog, UVM, formal verification methodologies.
• Proven experience in methodology development and tool automation.
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
• Good understanding of SoC architectures - ARM/RISC-V.
• Experience with at least two of: CPU subsystems, PCIe Gen3/Gen4/Gen5, DDR4/DDR5, LPDDR4X, MIPI DSI/CSI, Ethernet MAC, USB, Security/IPs.
• Exposure to emulation, hardware prototyping and post-silicon debug; FPGA-based acceleration.
• Python, TCL/TK, and C/C++ for automation and validation.
• Familiarity with Siemens/Cadence/Synopsys verification suites; Git/Perforce/SVN.

Responsibilities

• Verify complex subsystems and SoCs using constrained random, formal and C-based verification.
• Develop and maintain reusable UVM test benches and environments.
• Involve in RTL, power-aware and gate-level verification.
• Contribute to quality by using AI/ML-enabled verification methodologies.
• Collaborate with emulation and hardware prototyping teams to define a unified verification approach.
• Collaborate with architecture and design teams for first-silicon success.
• Mentor junior team members.

Skills

SystemVerilog

UVM

Formal verification

Tool automation

AI/ML-driven EDA

SoC architectures

CPU subsystems

PCIe Gen3/4/5

DDR4/DDR5

MIPI CSI/DSI

Ethernet MAC

USB

Security IPs

Emulation

Scripting (Python)

Git

Perforce

SVN

Cadence/Siemens/Synopsys

Education

BS/MS in Electrical Engineering

Tools

Git

Perforce

SVN

Cadence/Siemens/Synopsys tools

Job description

Microchip Technology Inc in Chandler, AZ is seeking an experienced verification engineer to verify next‑generation, highly secure, low‑power FPGA device products. The role emphasizes constrained random and formal verification, reusable UVM environments, and collaboration with architecture and design teams.

You will work across RTL, power-aware, and post-silicon debug, leveraging AI/ML-driven verification and cross‑functional teams. Mentoring junior engineers is part of the responsibilities.