Lead RTL Designer — AI-Driven NoC & Fabric

Architect Labs; Palo Alto (CA); On-site; USD 210,000 - 320,000; Full time

Job summary

Architect Labs is seeking a Founding Member of the Technical Staff to own the AI-driven RTL design for the on-chip interconnect fabric and NoC. You will define block-level microarchitecture, drive specifications, and deliver low-latency, high-bandwidth communication across SoC agents.

You’ll lead end-to-end RTL for NoC routers, crossbar switches, and fabric bridges, collaborating with DV, SW, and ML teams, and enabling FPGA prototyping for early validation.

Qualifications

• Bachelor’s, Master’s, or PhD in EE/CE or closely related field.
• 5+ years RTL design; 10+ years preferred; tapeout experience on interconnects or NoC fabrics.
• Deep ARM AMBA AXI4/AXI5, ACE-Lite, CHI knowledge and interface expertise.
• Experience designing crossbars, NoC routers, QoS, and deadlock-free interconnects.
• Strong SystemVerilog for synthesizable RTL, linting, and timing closure.

Responsibilities

• Own end-to-end on-chip fabric RTL development from NoC topology to timing closure.
• Design AMBA-based interconnect fabrics and network interfaces (AXI/CHI/ACE).
• Architect NoC routers/topologies with QoS, arbitration, and deadlock-free design.
• Build high-speed I/O fabric bridges and peer-to-peer DMA engines.
• Collaborate with DV, SW, and ML teams; support FPGA prototyping and validation.

Skills

RTL design

NoC/fabric design

AMBA protocol expertise

High-speed I/O integration

SystemVerilog

Python

Peer-to-peer DMA

Education

Bachelor’s/Master’s/PhD in Electrical/Computer Engineering

Tools

Vivado

SVA

Regression/EDA flow

Job description

Architect Labs is seeking a Founding Member of the Technical Staff to own the AI-driven RTL design for the on-chip interconnect fabric and NoC. You will define block-level microarchitecture, drive specifications, and deliver low-latency, high-bandwidth communication across SoC agents.

You’ll lead end-to-end RTL for NoC routers, crossbar switches, and fabric bridges, collaborating with DV, SW, and ML teams, and enabling FPGA prototyping for early validation.